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features ? high-density programmable logic 2000 pld gates 32 i/o pins, four dedicated inputs 96 registers high-speed global interconnect wide input gating for fast counters, state machines, address decoders, etc. small logic block size for random logic ? high-performance e 2 cmos ? technology f max = 125 mhz maximum operating frequency t pd = 7.5 ns propagation delay ttl compatible inputs and outputs electrically erasable and reprogrammable non-volatile 100% tested at time of manufacture unused product term shutdown saves power ? isplsi offers the following added features in-system programmable? (isp?) 5-volt only increased manufacturing yields, reduced time-to- market and improved product quality reprogram soldered device for faster prototyping ? offers the ease of use and fast system speed of plds with the density and flexibility of field programmable gate arrays complete programmable device can combine glue logic and structured designs enhanced pin locking capability three dedicated clock input pins synchronous and asynchronous clocks programmable output slew rate control to minimize switching noise flexible pin placement optimized global routing pool provides global interconnectivity ? plsi/isplsi development tools pds ? software easy to use pc windows? interface boolean logic compiler manual partitioning automatic place and route static timing table ispds+? software industry standard, third-party design environments schematic capture, state machine, hdl automatic partitioning and place and route comprehensive logic and timing simulation pc and workstation platforms functional block diagram clk a0 a1 a2 a3 a4 a5 a6 a7 b7 b6 b5 b4 b3 b2 b1 b0 output routing pool output routing pool global routing pool (grp) logic array dq dq dq dq glb 0139c1-isp description the isplsi and plsi 1016e are high-density programmable logic devices containing 96 registers, 32 universal i/o pins, four dedicated input pins, three dedicated clock input pins, one global oe input pin and a global routing pool (grp). the grp provides complete interconnectivity between all of these elements. the isplsi 1016e features 5-volt in-system programming and in-system diagnostic capabilities. the isplsi 1016e offers non-volatile on-the-fly reprogrammability of the logic, as well as the interconnect to provide truly reconfigurable systems. it is architecturally and parametrically compatible to the plsi 1016e device, but multiplexes four input pins to control in-system programming. a functional superset of the isplsi and plsi 1016 architecture, the isplsi and plsi 1016e devices add a new global output enable pin. the basic unit of logic on the isplsi and plsi 1016e devices is the generic logic block (glb). the glbs are labeled a0, a1...b7 (see figure 1). there are a total of 16 glbs in the isplsi and plsi 1016e devices. each glb has 18 inputs, a programmable and/or/exclusive or array, and four outputs which can be configured to be either combinatorial or registered. inputs to the glb come from the grp and dedicated inputs. all of the glb outputs are brought back into the grp so that they can be connected to the inputs of any other glb on the device. isplsi ? and plsi ? 1016e high-density programmable logic 1016e_04 copyright ? 1997 lattice semiconductor corp. all brand or product names are trademarks or registered trademarks of their respec tive holders. the specifications and information herein are subject to change without notice. lattice semiconductor corp., 5555 northeast moore ct., hillsboro, oregon 97124, u.s.a. tel. (503) 681-0118; 1-800-lattice; fax (503) 681-3037; http://www.latticesemi.com february 1997 1996 isp encyclopedia
2 1996 isp encyclopedia specifications isplsi and plsi 1016e functional block diagram figure 1. isplsi and plsi 1016e functional block diagram the devices also have 32 i/o cells, each of which is directly connected to an i/o pin. each i/o cell can be individually programmed to be a combinatorial input, registered input, latched input, output or bi-directional i/o pin with 3-state control. the signal levels are ttl compatible voltages and the output drivers can source 4 ma or sink 8 ma. each output can be programmed independently for fast or slow output slew rate to mini- mize overall output switching noise. eight glbs, 16 i/o cells, two dedicated inputs and one orp are connected together to make a megablock (see figure 1). the outputs of the eight glbs are connected to a set of 16 universal i/o cells by the orp. each isplsi and plsi 1016e device contains two megablocks. the grp has, as its inputs, the outputs from all of the glbs and all of the inputs from the bi-directional i/o cells. all of these signals are made available to the inputs of the glbs. delays through the grp have been equalized to minimize timing skew. clocks in the isplsi and plsi 1016e devices are se- lected using the clock distribution network. three dedicated clock pins (y0, y1 and y2) are brought into the distribution network, and five clock outputs (clk 0, clk 1, clk 2, ioclk 0 and ioclk 1) are provided to route clocks to the glbs and i/o cells. the clock distri- bution network can also be driven from a special clock glb (b0 on the isplsi and plsi 1016e devices). the logic of this glb allows the user to create an internal clock from a combination of internal signals within the device. i/o 0 i/o 1 i/o 2 i/o 3 goe 0/in 3 mode*/in 2 i/o 6 i/o 7 i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 i/o 15 i/o 31 i/o 30 i/o 29 i/o 28 i/o 27 i/o 26 i/o 25 i/o 24 i/o 23 i/o 22 i/o 21 i/o 20 i/o 19 i/o 18 i/o 17 i/o 16 *sdi/in 0 *sdo/in 1 i/o 4 i/o 5 *ispen/nc global routing pool (grp) clk 0 clk 1 clk 2 ioclk 0 ioclk 1 clock distribution network a0 a1 a2 a3 a4 a5 a6 a7 b7 b6 b5 b4 b3 b2 b1 b0 output routing pool (orp) generic logic blocks (glbs) megablock output routing pool (orp) input bus lnput bus **note: y1 and reset are multiplexed on the same pin *sclk/y2 y0 y1** * isplsi 1016e only 0139b(1a)-isp
3 1996 isp encyclopedia specifications isplsi and plsi 1016e absolute maximum ratings 1 supply voltage v cc ................................. -0.5 to +7.0v input voltage applied ........................ -2.5 to v cc +1.0v off-state output voltage applied ..... -2.5 to v cc +1.0v storage temperature ................................ -65 to 150 c case temp. with power applied .............. -55 to 125 c max. junction temp. (t j ) with power applied ... 150 c 1. stresses above those listed under the absolute maximum ratings may cause permanent damage to the device. functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specifica tion is not implied (while programming, follow the programming specifications). dc recommended operating conditions t a = 0 c to + 70 c t a = -40 c to + 85 c symbol table 2-0005/1016e v cc v ih v il parameter supply voltage input high voltage input low voltage min. max. units 4.75 4.5 2.0 0 5.25 5.5 v cc +1 0.8 v v v v commercial industrial capacitance (t a =25 o c, f=1.0 mhz) data retention specifications c symbol table 2-0006/1016e c parameter y0 clock capacitance 12 units typical test conditions 1 2 8 dedicated input, i/o, y1, y2, y3, clock capacitance (commercial/industrial) pf pf v = 5.0v, v = 2.0v v = 5.0v, v = 2.0v cc cc pin pin table 2-0008/1016e parameter plsi erase/reprogram cycles 100 data retention minimum maximum units isplsi erase/reprogram cycles 20 10000 cycles years cycles
4 1996 isp encyclopedia specifications isplsi and plsi 1016e switching test conditions figure 2. test load dc electrical characteristics over recommended operating conditions input pulse levels table 2-0003/1016e input rise and fall time 10% to 90% input timing reference levels ouput timing reference levels output load gnd to 3.0v 1.5v 1.5v see figure 2 3-state levels are measured 0.5v from steady-state active level. -125 -100, -80 2 ns 3 ns output load conditions (see figure 2) test condition r1 r2 cl a 470 w 390 w 35pf b 390 w 35pf 470 w 390 w 35pf active high active low c 470 w 390 w 5pf 390 w 5pf active low to z at v +0.5v ol active high to z at v -0.5v oh table 2-0004/1016e + 5v r 1 r 2 c l * device output test point * c l includes test fixture and probe capacitance. 0213a v ol symbol 1. one output at a time for a maximum duration of one second. v = 0.5v was selected to avoid test problems by tester ground degradation. guaranteed but not 100% tested. 2. measured using four 16-bit counters. 3. typical values are at v = 5v and t = 25 c. 4. maximum i varies widely with specific device configuration and operating frequency. refer to the power consumption section of this data sheet and thermal management section of the lattice semiconductor data book to estimate maximum i . table 2-0007/1016e 1 v oh i ih i il i il-isp parameter i il-pu i os 2, 4 i cc output low voltage output high voltage input or i/o high leakage current input or i/o low leakage current ispen input low leakage current i/o active pull-up current output short circuit current operating power supply current i = 8 ma i = -4 ma 3.5v v v 0v v v (max.) 0v v v 0v v v v = 5v, v = 0.5v v = 0.5v, v = 3.0v f = 1 mhz ol oh in il in cc in il in il cc out clock il ih condition min. typ. max. units 3 2.4 90 90 0.4 10 -10 -150 -150 -200 v v m a m a m a m a ma ma ma cc a out cc cc commercial industrial
5 1996 isp encyclopedia specifications isplsi and plsi 1016e external timing parameters over recommended operating conditions t pd1 units -125 min. test cond. 1. unless noted otherwise, all parameters use the grp, 20 ptxor path, orp and y0 clock. 2. refer to timing model in this data sheet for further details. 3. standard 16-bit counter using grp feedback. 4. reference switching test conditions section. table 2-0030-16/125,100, 80 1 4 3 1 tsu2 + tco1 ( ) -100 min. max. max. description # 2 parameter a 1 data prop. delay, 4pt bypass, orp bypass 7.5 10.0 ns t pd2 a 2 data prop. delay, worst case path ns f max a 3 clk. frequency with int. feedback 125 100 mhz f max (ext.) 4 clk. frequency with ext. feedback mhz f max (tog.) 5 clk. frequency, max. toggle mhz t su1 6 glb reg. setup time before clk., 4 pt bypass ns t co1 a 7 glb reg. clk. to output delay, orp bypass ns t h1 8 glb reg. hold time after clk., 4 pt bypass 0.0 ns t su2 9 glb reg. setup time before clk. 5.5 ns t co2 10 glb reg. clk. to output delay ns t h2 11 glb reg. hold time after clk. 0.0 ns t r1 a 12 ext. reset pin to output delay ns t rw1 13 ext. reset pulse duration 5.0 ns t ptoeen b 14 input to output enable ns t ptoedis c 15 input to output disable ns t wh 18 ext. sync. clk. pulse duration, high 3.0 4.0 ns t wl 19 ext. sync. clk. pulse duration, low 3.0 4.0 ns t su3 20 i/o reg. setup time before ext. sync. clk. (y2, y3) 3.0 ns t h3 21 i/o reg. hold time after ext. sync. clk. (y2, y3) 0.0 ns 100 167 5.0 4.5 5.5 10.0 12.0 12.0 10.0 77 125 7.0 0.0 8.0 0.0 6.5 3.5 0.0 13.0 5.0 6.0 13.5 15.0 15.0 ( ) 1 twh + tw1 t goeen b 16 global oe output enable ns 7.0 9.0 t goedis c 17 global oe output disable ns 7.0 9.0 -80 min. max. 15.0 18.5 84.0 57.0 100 8.5 8.0 0.0 9.5 9.5 0.0 17.0 10.0 20.0 20.0 10.5 10.5 5.0 0.0 4.5 5.0
6 1996 isp encyclopedia specifications isplsi and plsi 1016e internal timing parameters 1 t iobp 1. internal timing parameters are not tested and are for reference only. 2. refer to timing model in this data sheet for further details. 3. the xor adjacent path can only be used by lattice hard macros. table 2-0036-16/125,100, 80 inputs units -125 min. -100 min. max. max. description # 2 parameter 22 i/o register bypass 0.4 ns t iolat 23 i/o latch delay 2.4 ns t grp1 29 grp delay, 1 glb load 1.9 ns glb t 1ptxor 36 1 product term/xor path delay 6.1 ns t 20ptxor 37 20 product term/xor path delay 6.1 ns t xoradj 38 xor adjacent path delay 6.6 ns t gbp 39 glb register bypass delay 1.6 ns t gsu 40 glb register setup time before clock 0.2 ns t gh 41 glb register hold time after clock 2.5 ns t gco 42 glb register clock to output delay 1.9 ns 3 t gro 43 glb register reset to output delay 6.3 ns t ptre 44 glb product term reset to register delay 5.1 ns t ptoe 45 glb product term output enable to i/o cell delay 7.1 ns t ptck 46 glb product term clock delay 4.8 5.3 ns orp 0.3 1.8 grp 1.8 t 4ptbpc 34 4 product term bypass path delay (combinatorial) 5.7 ns 4.4 4.4 4.4 1.0 3.9 t 4ptbpr 35 4 product term bypass path delay (registered) 5.6 ns 3.9 0.2 1.5 1.8 4.4 3.5 5.5 3.2 3.5 t orp 47 orp delay 1.0 ns t orpbp 48 orp bypass delay 0.0 ns 1.0 0.0 t iosu 24 i/o register setup time before clock 3.0 3.5 ns t ioh 25 i/o register hold time after clock -0.3 -0.4 ns t ioco 26 i/o register clock to out delay 5.0 ns 4.0 t ior 27 i/o register reset to out delay 5.0 ns 4.0 t din 28 dedicated input delay 2.6 ns 2.2 -80 min. max. 0.6 3.6 4.5 -0.6 7.5 7.5 3.9 2.9 7.1 8.2 8.3 1.9 8.1 7.3 -0.6 4.3 2.9 7.0 7.2 9.7 6.8 7.5 1.5 0.0 t grp16 32 grp delay, 16 glb loads 3.1 ns t grp4 30 grp delay, 4 glb loads 2.2 ns 2.4 1.9 t grp8 31 grp delay, 8 glb loads 2.5 ns 2.1 4.7 3.3 3.8
7 1996 isp encyclopedia specifications isplsi and plsi 1016e internal timing parameters 1 t ob 1. internal timing parameters are not tested and are for reference only. 2. refer to timing model in this data sheet for further details. table 2-0037-16/125,100,80 outputs units -125 min. -100 min. max. max. description # 2 parameter 49 output buffer delay 1.7 ns t gy0 54 clock delay, y0 to global glb clock line (ref. clock) 1.3 1.4 1.4 ns global reset 1.4 t sl 50 output slew limited delay adder 10.0 ns 10.0 t oen 51 i/o cell oe to output enabled 5.3 ns 4.3 clocks 1.3 t gr 59 global reset to glb and i/o registers 5.5 ns 3.2 t odis 52 i/o cell oe to output disabled 5.3 ns 4.3 t goe 53 global output enable 3.7 ns 2.7 t gy1/2 55 clock delay, y1 or y2 to global glb clock line 2.3 2.4 2.9 ns 2.7 t gcp 56 clock delay, clock glb to global glb clock line 0.8 0.8 1.8 ns 1.8 t ioy1/2 57 clock delay, y1 or y2 to i/o cell global clock line 0.0 0.0 0.4 ns 0.3 t iocp 58 clock delay, clock glb to i/o cell global clock line 0.8 0.8 1.8 ns 1.8 -80 min. max. 3.0 10.0 6.4 6.4 4.1 4.5 2.1 2.1 3.6 4.4 1.2 2.7 0.0 0.6 1.2 2.7
8 1996 isp encyclopedia specifications isplsi and plsi 1016e isplsi and plsi 1016e timing model glb reg delay i/o pin (output) orp delay feedback reg 4 pt bypass 20 pt xor delays control pts input register clock distribution i/o pin (input) y0 y1,2 d q glb reg bypass orp bypass dq rst re oe ck i/o reg bypass i/o cell orp glb grp i/o cell #23 - 27 #30 #35 #36-38 #55-58 #44-46 #54 #47 #48 reset ded. in goe 0 #28 #22 rst #59 #59 #39 #40-43 #51, 52 0491-16 comb 4 pt bypass #34 #53 grp loading delay #29, 31, 32 #49, 50 derivations of t su, t h and t co from the product term clock 1 = = = = t su logic + reg su - clock (min) ( t iobp + t grp4 + t 20ptxor) + ( t gsu) - ( t iobp + t grp4 + t ptck(min)) (#22 + #30 + #37) + (#40) - (#22 + #30 + #46) (0.3 + 1.9 + 4.4) + (0.2) - (0.3 + 1.9 + 3.2) 1.4 ns = = = = t h clock (max) + reg h - logic ( t iobp + t grp4 + t ptck(max)) + ( t gh) - ( t iobp + t grp4 + t 20ptxor) (#22 + #30 + #46) + (#41) - (#22 + #30 + #37) (0.3 + 1.9 + 3.5) + (1.5) - (0.3 + 1.9 + 4.4) 0.6 ns = = = = t co clock (max) + reg co + output ( t iobp + t grp4 + t ptck(max)) + ( t gco) + ( t orp + t ob) (#22 + #30 + #46) + (#42) + (#47 + #49) (0.3 + 1.9 + 3.5) + (1.8) + (1.0 + 1.4) 9.9 ns table 2-0042-16 derivations of t su, t h and t co from the clock glb 1 = = = = t su logic + reg su - clock (min) ( t iobp + t grp4 + t 20ptxor) + ( t gsu) - ( t gy0(min) + t gco + t gcp(min)) (#22 + #30 + #37) + (#40) - (#54 + #42 + #56) (0.3 + 1.9 + 4.4) + (0.2) - (1.3 + 1.8 + 0.8) 2.9 ns = = = = t h clock (max) + reg h - logic ( t gy0(max) + t gco + t gcp(max)) + ( t gh) - ( t iobp + t grp4 + t 20ptxor) (#54 + #42 + #56) + (#41) - (#22 + #30 + #37) (1.3 + 1.8 + 1.8) + (1.5) - (0.3 + 1.9 + 4.4) -0.2 ns = = = = t co clock (max) + reg co + output ( t gy0(max) + t gco + t gcp(max)) + ( t gco) + ( t orp + t ob) (#54 + #42 + #56) + (#42) + (#47 + #49) (1.3 + 1.8 + 1.8) + (1.8) + (1.0 + 1.4) 9.1 ns 1. calculations are based upon timing specifications for the isplsi and plsi 1016e- 125
9 1996 isp encyclopedia specifications isplsi and plsi 1016e power consumption power consumption in the isplsi and plsi 1016e device depends on two primary factors: the speed at which the device is operating and the number of product terms used. figure 3 shows the relationship between power and operating speed. 80 110 0 20 40 60 80 100 120 140 f max (mhz) i cc (ma) notes: configuration of four 16-bit counters typical current at 5v, 25 c isplsi and plsi 1016e 100 0127b-16-80-isp/1016 i cc can be estimated for the isplsi and plsi 1016e using the following equation: i cc (ma) = 23 + (# of pts * 0.52) + (# of nets * max freq * 0.004) where: # of pts = number of product terms used in design # of nets = number of signals used in device max freq = highest clock frequency to the device (in mhz) the i cc estimate is based on typical conditions (v cc = 5.0v, room temperature) and an assumption of four glb loads on average exists and the device is filled with four 16-bit counters. these values are for estimates only. since the value of i cc is sensitive to operating conditions and the program in the device, the actual i cc should be verified. 120 130 90 figure 3. typical device power consumption vs fmax maximum grp delay vs glb loads glb load 1 3 1 4 8 16 grp delay (ns) 2 16e grp/glb.eps isplsi and plsi 1016e-125 isplsi and plsi 1016e-100 12 isplsi and plsi 1016e-80
10 1996 isp encyclopedia specifications isplsi and plsi 1016e in-system programmability the isplsi devices are the in-system programmable versions of the lattice semiconductor high-density pro- grammable large scale integration (plsi) devices. by integrating all the high voltage programming circuitry on- chip, programming can be accomplished by simply shifting data into the device. once the function is programmed, the non-volatile e 2 cmos cells will not lose the pattern even when the power is turned off. all necessary programming is done via five ttl level logic interface signals. these five signals are fed into the on-chip programming circuitry where a state machine controls the programming. the simple signals for the interface include isp enable ( ispen ), serial data in (sdi), serial data out (sdo), serial clock (sclk) and mode (mode) control. figure 4 illustrates the block diagram of one possible scheme for programming the isplsi de- vices. for details on the operation of the internal state machine and programming of the device, please refer to the isp architecture and programming section of the 1996 lattice data book. the device identifier for the isplsi 1016e is 0000 1011 (0b hex). this code is the unique device identifier which is generated when a read id command is performed. figure 4. isp programming interface ispgds ispgal isplsi sclk mode sclk mode sdi sdo sdo sdo sdi sdi ispen sclk mode sdo sdi mode sclk ispen 5-wire isp programming interface isplsi sclk mode sdi sdo ispen 0294b
11 1996 isp encyclopedia specifications isplsi and plsi 1016e isplsi 1016e shift register layout e 2 cmos cell array high order shift register low order shift register 79... 159... ...0 ...80 d a t a d a t a data in (sdi) sdo 109 . . . address shift register . . . 0 sdo sdi 0182b-16 note: a logic 1 in the address shift register bit position enables the row for programming or verification. a logic 0 disables it.
12 1996 isp encyclopedia specifications isplsi and plsi 1016e input - this pin performs two functions. when ispen is logic low, it functions as an input pin to load programming data into the device. it is a dedicated input pin when ispen is logic high.sdi/in0 also is used as one of the two control pins for the isp state machine. dedicated clock input. this clock input is connected to one of the clock inputs of all the glbs on the device. this pin performs two functions: input - dedicated in-system programming enable input pin. this pin is brought low to enable the programming mode. the mode, sdi, sdo and sclk controls become active. this is a dual function pin. it can be used either as global output enable for all i/o cells or it can be used as a dedicated input pin. input/output pins - these are the general purpose i/o pins used by the logic array. name table 2-0002c-16-isp description i/o 0 - i/o 3 i/o 4 - i/o 7 i/o 8 - i/o 11 i/o 12 - i/o 15 i/o 16 - i/o 19 i/o 20 - i/o 23 i/o 24 - i/o 27 i/o 28 - i/o 31 goe 0/in 3 y1/ reset y0 sdi*/in 0 ispen **/nc mode*/in 2 input - this pin performs two functions. when ispen is logic low, it functions as a pin to control the operation of the isp state machine. it is a dedicated input pin when ispen is logic high. gnd vcc vcc - dedicated clock input. this clock input is brought into the clock distribution network, and can optionally be routed to any glb and/or i/o cell on the device. output/input - this pin performs two functions. when ispen is logic low, it functions as an ouput pin to read serial shift register data. it is a dedicated input pin when ispen is logic high. sdo*/in 1 input - this pin performs two functions. when ispen is logic low, it functions as a clock pin for the serial shift register. it is a dedicated clock input when ispen is logic high. this clock input is brought into the clock distribution network, and can optionally be routed to any glb and/or i/o cell on the device. sclk*/y2 ground (gnd) - active low (0) reset pin which resets all of the glb and i/o registers in the device. plcc pin numbers 15, 19, 25, 29, 37, 41, 3, 7, 16, 20, 26, 30, 38, 42, 4, 8, 17, 21, 27, 31, 39, 43, 5, 9, 18, 22, 28, 32, 40, 44, 6, 10 2 35 11 14 13 36 1, 12, 24 33 23 34 * isplsi 1016e only ** ispen for isplsi 1016e; nc for plsi 1016e must be left floating or tied to vcc, must not be grounded or tied to any other signal. tqfp pin numbers 9, 13, 19, 23, 31, 35, 41, 1, 10, 14, 20, 24, 32, 36, 42, 2, 11, 15, 21, 25, 33, 37, 43, 3, 12, 16, 22, 26, 34, 38, 44, 4 40 29 5 8 7 30 17, 6, 18 27 39 28 pin description
13 1996 isp encyclopedia specifications isplsi and plsi 1016e pin configurations isplsi and plsi 1016e 44-pin plcc pinout diagram ** pins have dual function capability which is software selectable. i/o 18 i/o 17 i/o 16 *mode/in 2 y1/reset vcc *sclk/y2 i/o 15 i/o 14 i/o 13 i/o 12 i/o 28 i/o 29 i/o 30 i/o 31 y0 vcc *ispen/nc *sdi/in 0 i/o 0 i/o 1 i/o 2 i/o 27 i/o 26 i/o 25 i/o 24 **goe 0/in 3 gnd i/o 23 i/o 22 i/o 21 i/o 20 i/o 19 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 gnd *sdo/in 1 i/o 8 i/o 9 i/o 10 i/o 11 isplsi 1016e plsi 1016e top view 7 8 9 10 12 11 13 14 15 16 17 39 38 37 36 35 34 33 32 31 30 29 6 18 5 19 4 20 3 21 2 22 1 23 44 24 43 25 42 26 41 27 40 28 0123a-isp1016 * pins have dual function capability for isplsi 1016e only (except pin 13, which is ispen only). isplsi 1016e 44-pin tqfp pinout diagram i/o 18 i/o 17 i/o 16 *mode/in 2 y1/reset vcc *sclk/y2 i/o 15 i/o 14 i/o 13 i/o 12 i/o 28 i/o 29 i/o 30 i/o 31 y0 vcc ispen *sdi/in 0 i/o 0 i/o 1 i/o 2 i/o 27 i/o 26 i/o 25 i/o 24 **goe 0/in 3 gnd i/o 23 i/o 22 i/o 21 i/o 20 i/o 19 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 gnd *sdo/in 1 i/o 8 i/o 9 i/o 10 i/o 11 isplsi 1016e top view 1 2 3 4 6 5 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 44 12 43 13 42 14 41 15 40 16 39 17 38 18 37 19 36 20 35 21 34 22 0851-16e/tqfp * pins have dual function capability. ** pins have dual function capability which is software selectable.
14 1996 isp encyclopedia specifications isplsi and plsi 1016e part number description isplsi and plsi 1016e ordering information device number grade blank = commercial i = industrial isplsi plsi 1016e xxx x xxx x speed power l = low package j = plcc t44 = tqfp device family 0212/1016e (is)plsi 125 100 80 = = = 125 mhz f max 100 mhz f max 84 mhz f max 84 84 44-pin plcc 15 15 isplsi 1016e-80lj 44-pin tqfp isplsi 1016e-80lt44 plsi table 2-0041a/1016e 125 100 44-pin plcc 7.5 10 plsi 1016e-125lj 44-pin plcc plsi 1016e-100lj 84 15 44-pin plcc plsi 1016e-80lj family f max (mhz) 125 125 100 ordering number package 44-pin plcc 44-pin tqfp t pd (ns) 7.5 7.5 10 isplsi isplsi 1016e-125lj isplsi 1016e-125lt44 44-pin plcc isplsi 1016e-100lj 100 44-pin tqfp 10 isplsi 1016e-100lt44 commercial table 2-0041b/1016e family f max (mhz) 84 84 ordering number package 44-pin plcc 44-pin tqfp t pd (ns) 15 15 isplsi isplsi 1016e-80lji isplsi 1016e-80lt44i industrial
copyright ? 1997 lattice semiconductor corporation. e 2 cmos, gal, ispgal, isplsi, plsi, pds, silicon forest, ultramos, lattice semiconductor, l (stylized) lattice semiconductor corp., l (stylized) and lattice (design) are registered trademarks of lattice semiconductor corporation. generic array logic, isp, ispate, ispcode, ispdownload, ispgds, ispds, ispds+, ispstarter, ispstream, isptest, ispturbo, latch-lock, pds+, rft, total isp and twin glb are trademarks of lattice semiconductor corporation. isp is a service mark of lattice semiconductor corporation. all brand names or product names mentioned are trademarks or registered trademarks of their respective holders. lattice semiconductor corporation (lsc) products are made under one or more of the following u.s. and international patents: 4,761,768 us, 4,766,569 us, 4,833,646 us, 4,852,044 us, 4,855,954 us, 4,879,688 us, 4,887,239 us, 4,896,296 us, 5,130,574 us, 5,138,198 us, 5,162,679 us, 5,191,243 us, 5,204,556 us, 5,231,315 us, 5,231,316 us, 5,237,218 us, 5,245,226 us, 5,251,169 us, 5,272,666 us, 5,281,906 us, 5,295,095 us, 5,329,179 us, 5,331,590 us, 5,336,951 us, 5,353,246 us, 5,357,156 us, 5,359,573 us, 5,394,033 us, 5,394,037 us, 5,404,055 us, 5,418,390 us, 5,493,205 us, 0194091 ep, 0196771b1 ep, 0267271 ep, 0196771 uk, 0194091 gb, 0196771 wg, p3686070.0-08 wg. lsc does not represent that products described herein are free from patent infringement or from any third-party right. the specifications and information herein are subject to change without notice. lattice semiconductor corporation (lsc) reserves the right to discontinue any product or service without notice and assumes no obligation to correct any errors contained herein or to advise any user of this document of any correction if such be made. lsc recommends its customers obtain the latest version of the relevant information to establish, before ordering, that the information being relied upon is current. lsc warrants performance of its products to current and applicable specifications in accordance with lscs standard warranty. testing and other quality control procedures are performed to the extent lsc deems necessary. specific testing of all parameters of each product is not necessarily performed, unless mandated by government requirements. lsc assumes no liability for applications assistance, customers product design, software performance, or infringements of patents or services arising from the use of the products and services described herein. lsc products are not authorized for use in life-support applications, devices or systems. inclusion of lsc products in such applications is prohibited. lattice semiconductor corporation 5555 northeast moore court hillsboro, oregon 97124 u.s.a. tel.: (503) 681-0118 fax: (503) 681-3037 http://www.latticesemi.com february 1997

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